MIM (metal-insulator-metal) capacitors based on high-K dielectrics play an important role for next generation Integrated Discretes (IDs) devices. Such Integrated Discretes devices comprise for instance capacitors, resistors and ESD protection diodes.
US 2008/0001292 A1 describes an electronic component with an integrated thin-film MIM capacitor structure on a substrate. The thin-film capacitor includes a pyrochlore or perovskite alkali earth dielectric layer between a plurality of electrode layers. A pyrochlore or perovskite hydrogen-gettering cover layer is deposited over the thin-film capacitor. It is in different embodiments made of (BaxSry)TiO3 (BST), BaTi03, CaTi03, SrTi03, BeTi03, MbTi03 or a mix of these materials. The hydrogen-gettering cover layer prevents hydrogen from reacting with and degrading the properties of the dielectric material. A hermetic seal layer is then deposited over the cover layer by a hydrogen-producing method, without causing damage to the dielectric layer.
It is briefly mentioned in US 2008/0001292 A1 that other passive components such as inductors, resistors and capacitors can be integrated into the electronic component on the same substrate.
For saving chip area, it would be desirable to provide an electronic component with a three-dimensional arrangement of capacitors on one hand and resistors and/or inductors on the other hand, and optionally with other active or passive circuit elements, i.e., stacked on top of each other.
It would also be desirable to be able to provide such a three-dimensional arrangement when using cover layers made of different materials than those known from US 2008/0001292 A1. In particular, using a cover layer made of lead zirconate titanate (PbxZrzTi1-zO3, PZT) raises difficulties. Issues of process reliability have been observed when using such a dielectric layers as a cover layer in a stacked arrangement of passives comprising a capacitor and a resistor on top of the capacitor. The difficulties arise in particular in a desired precise control of the electrical resistance of a resistor layer during manufacture of the device.